1. Field of Invention
The present invention relates to a circuit board and a fabricating process thereof. More particularly, the present invention relates to a circuit board with an embedded passive component and a fabricating process thereof.
2. Description of Related Art
Due to the increasingly greater degree of integration of electronic products, circuit layers of circuit boards applied in highly integrated electronic products have changed from single or double layers to six layers, eight layers, or even more than ten layers, so that electronic devices can be mounted more densely on circuit boards. However, with the increase of layer counts of circuit boards and the density of the lines, influences to electrical signals transmitted in circuit boards caused by resistance-capacitance delay (RC delay) or cross-talk become more and more obvious. Therefore, additional passive components must be disposed in limited areas of circuit boards to improve the electrical properties thereof.
As described above, besides passive components, various electronic devices are further arranged in limited layout areas of circuit boards. However, the specified passive components with particular electrical values may not completely meet a particular given circuit design. Therefore, it is practical to fabricate passive components directly in circuit boards. Moreover, passive components in circuit boards can also adjust the electrical values thereof depending on layout design, circuit board material selection, and the like.
FIGS. 1A-1E show schematic sectional views of a conventional process for fabricating a circuit board with an embedded passive component. First, referring to FIG. 1A, a first copper foil layer 110 is provided, and a capacitive material is coated on the overall first copper foil layer 110, so as to form a capacitive material layer 120. Next, referring to FIG. 1B, a second copper foil layer 130 is formed on the capacitive material layer 120 in a lamination manner. Then, referring to FIG. 1C, the second copper foil layer 130 in FIG. 1B undergoes a lithographic process and an etching process to form a second circuit layer 130′. Then, referring to FIG. 1D, the capacitive material layer 120 in FIG. 1C undergoes a patterning process, for example, including a lithographic process and an etching process, to form a patterned capacitive material layer 120′. Next, a multilayer circuit board L and a dielectric layer 140 are provided, and the structure formed by the above processes, the multilayer circuit board L, and the dielectric layer 140 are laminated, wherein the patterned capacitive material layer 120′ and the second circuit layer 130′ are embedded in the dielectric layer 140. Further, referring to FIG. 1E, the first copper foil layer 110 undergoes the patterning process, for example, including a lithographic process and an etching process, to form a first circuit layer 110′. Thereafter, a plurality of conductive vias (not shown) is formed in the structure formed by the above processes to electrically connect the multilayer circuit board L and the first circuit layer 110′.
However, only single layer capacitance devices can be fabricated through conventional circuit board processes, and just one kind of passive component (referred to as a capacitance device herein) can be embedded in the single layer. Moreover, each capacitance device occupies a large area, such that the area for accommodating other integrated circuit devices is relatively reduced.